Hello Dr. @jeff.dietiker, thank you for your reply. I’ve set up a new case, coarsened cell width to double-size, and here are my observations.
A. As suggested, when I use Mixed wall → No-slip → tangential velocity, BC works, the direction is also correct. When I see case setup in an editor, bc_type(1, 2, 3, 4)=‘PSW’ and there is no mention of bc_hw_g. Please see images on attached slide for your reference.
B. Would this BC setup work on an STL boundary (say, stepped cylinder)? If yes, how can we ramp up this velocity linearly with time?
C. I’ve set 5 m/s and time to 20 sec for steady-state. All time-steps until 4.8726s took ~15 inner iterations and reached E-04 residual. After this point, each time-step took max iterations=500 and residual never went below E-03. How can we avoid this?
Less important:
D. Whenever I include more than one output VTK, only the last VTK file is written out. How can we avoid this?
Thank you.